Transistors can be divided into two main types: bipolar junction transistors and field-effect transistors. Both types share a common structure comprising three electrodes with a semi-conductive material disposed therebetween in a channel region. The three electrodes of a bipolar junction transistor are known as the emitter, collector and base, whereas in a field-effect transistor the three electrodes are known as the source, drain and gate. Bipolar junction transistors may be described as current-operated devices as the current between the emitter and collector is controlled by the current flowing between the base and emitter. In contrast, field-effect transistors may be described as voltage-operated devices as the current flowing between source and drain is controlled by the voltage between the gate and the source.
Transistors can also be classified as p-type and n-type according to whether they comprise semi-conductive material which conducts positive charge carriers (holes) or negative charge carriers (electrons) respectively. The semi-conductive material may be selected according to its ability to accept, conduct, and donate charge. The ability of the semi-conductive material to accept, conduct, and donate holes or electrons can be enhanced by doping the material. The material used for the source and drain electrodes can also be selected according to its ability to accept and injecting holes or electrodes. For example, a p-type transistor device can be formed by selecting a semi-conductive material which is efficient at accepting, conducting, and donating holes, and selecting a material for the source and drain electrodes which is efficient at injecting and accepting holes from the semi-conductive material. Good energy-level matching of the Fermi-level in the electrodes with the HOMO level of the semi-conductive material can enhance hole injection and acceptance. In contrast, an n-type transistor device can be formed by selecting a semi-conductive material which is efficient at accepting, conducting, and donating electrons, and selecting a material for the source and drain electrodes which is efficient at injecting electrons into, and accepting electrons from, the semi-conductive material. Good energy-level matching of the Fermi-level in the electrodes with the LUMO level of the semi-conductive material can enhance electron injection and acceptance.
Transistors can be formed by depositing the components in thin films to form thin film transistors. When an organic material is used as the semi-conductive material in such a device, it is known as an organic thin film transistor (OTFT). OTFTs may be manufactured by low cost, low temperature methods such as solution processing. Moreover, OTFTs are compatible with flexible plastic substrates, offering the prospect of large-scale manufacture of OTFTs on flexible substrates in a roll-to-roll process.
Various arrangements for organic thin film transistors are known. One such device is an insulated gate field-effect transistor which comprises source and drain electrodes with a semi-conductive material disposed therebetween in a channel region, a gate electrode disposed adjacent the semi-conductive material and a layer of insulating material disposed between the gate electrode and the semi-conductive material in the channel region.
An example of such an organic thin film transistor is shown in FIG. 1. The illustrated structure may be deposited on a substrate (not shown) and comprises source and drain electrodes 2, 4 which are spaced apart with a channel region 6 located therebetween. An organic semiconductor (OSC) 8 is deposited in the channel region 6 and may extend over at least a portion of the source and drain electrodes 2, 4. An insulating layer 10 of dielectric material is deposited over the organic semi-conductor 8 and may extend over at least a portion of the source and drain electrodes 2, 4. Finally, a gate electrode 12 is deposited over the insulating layer 10. The gate electrode 12 is located over the channel region 6 and may extend over at least a portion of the source and drain electrodes 2, 4.
The structure described above is known as a top-gate organic thin film transistor as the gate is located on a top side of the device. Alternatively, it is also known to provide the gate on a bottom side of the device to form a so-called bottom-gate organic thin film transistor.
One problem with organic thin film transistors is parasitic gate capacitance and gate leakage to the source and drain. In prior art arrangements, such as that illustrated in FIG. 1, this problem may be solved by increasing the thickness of gate insulating material. However, if the thickness of the gate insulating material is increased adjacent the channel region, then a larger voltage will be required to turn on the transistor. Accordingly, a preferred solution would be to only increase the thickness of the gate insulating material in the gate and source/drain overlap area. Such a solution is known from the documents discussed below.
US 2006/060855 discloses an extra insulating layer only in the region where the gate and the source/drain electrodes overlap. This extra insulating layer is deposited over the main gate dielectric layer and patterned prior to deposition of the gate.
US 2006/220022 discloses a gate insulating layer having varying thickness. The gate insulating layer is thinner in a central region thereof over the channel and is thicker at peripheral regions where the gate overlaps the source/drain.
One possible problem with both the aforementioned arrangements is that they require extra dielectric material to be deposited over the organic semi-conductive layer which may damage the organic semi-conductive layer. Another possible problem with both the aforementioned arrangements is that it is difficult to align all the overlying layers in the device, such as alignment of the gate with the channel region between the source and drain. Furthermore, containment of the organic semi-conductive material in the channel region may also be a problem.
An additional problem with the arrangement disclosed in US 2006/060855 is that it requires deposition of an additional layer of dielectric material over the gate dielectric layer and patterning of the additional layer by, for example, etching. This may cause damage to the underlying gate dielectric layer in the channel region affecting the performance of the transistor.
An additional problem with the arrangement disclosed in US 2006/220022 is that the gate dielectric layer of varying thickness may be difficult to form in a reproducible manner in order to form devices having uniform properties.
It is one aim of embodiments of the present invention to provide a solution to one or more of the problems discussed above.